1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a contactless EPROM cell array structure which utilizes a field oxide bit line isolation scheme that eliminates the requirement for the complex virtual ground row decoders normally associated with flash EPROM arrays.
2. Discussion of the Prior Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally-stored binary data is retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written into the EPROM by deactivating the chip select line in order to switch the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each data storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs is connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected storage register is provided to the databus.
An electrically erasable programmable read only memory (EEPROM) is a variation of the EPROM design wherein binary data is read, written and erased electrically. A single operation erases the selected data storage register. In the case of the so-called "flash" EPROM device, all data storage registers in the memory array ar electrically erased in a single operation.
The state of the art of flash EPROM cells is represented by the Intel ETOX cell, which is illustrated in FIGS. 1-3. FIG. 1 shows a portion of a typical T-shaped layout of an ETOX cell array with one drain contact 22a sharing two cells. FIG. 2 shows a cross-section of an ETOX cell which is taken along line A--A, i.e. along a polysilicon (poly 2) word line 16 in the portion of the ETOX array illustrated in FIG. 1. FIG. 3 shows a cross-section of an ETOX cell taken along line B--B, i.e. along a N+ bit line in the portion of the ETOX array illustrated in FIG. 1.
As shown in the FIG. 1 layout, and as stated above, the ETOX array is based on the standard "T-shaped" EPROM cell. As shown in FIGS. 2 and 3, it is implementated utilizing a very thin gate oxide 12 (about 100.ANG.) and graded N+/N- implants in the source regions 14 to prevent disturbances due to band-to-band tunneling in the erase mode.
As shown in FIG. 4A, the ETOX flash cell 10 is written in the conventional EPROM manner. That is, hot electrons are injected from the source region 14 into the polysilicon (poly 1) floating gate 18 when the poly 2 word line 16 and the N+ bit line 20 are both high.
As shown in FIG. 4B, erasing the ETOX cell 10 is performed by tunneling electrons from the floating gate 18 through the thin oxide 12 close to the source region 14 when the source region 14 is high, the drain 20 is floating and the word line 16 is low.